（設計技術統括部）Test Chip Design Engineer (Physical Design & PPA Analysis)
- 職務内容
- Rapidus is a leading foundry at the forefront of semiconductor innovation, enabling the next generation of integrated circuits. We are seeking a highly skilled and experienced Test Chip Design Engineer to join our team. In this role, you will be responsible for the physical design and PPA (Power, Performance, Area) analysis of cutting-edge test chips, critical for validating and characterizing our advanced process technologies.
You will play a pivotal role in bridging the gap between process development and product design, ensuring our technology offerings meet the demanding requirements of our global customers. This position offers a unique opportunity to work with the latest process nodes and design methodologies, contributing directly to the future of semiconductor manufacturing.
Key Responsibilities
As a Test Chip Design Engineer, your responsibilities will include:
- Test Chip Physical Design and PPA Analysis:
- Backend (BE) Implementation and Related Flow Development: Drive the full backend implementation flow, from chip-level planning and PG (Power/Ground) network design to floorplan, place, CTS (Clock Tree Synthesis), route, power analysis (PDNA sign-off), and comprehensive physical verification.
- Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively.
- Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies.
- Collaborate closely with process development teams, circuit design teams, and EDA vendors to define and implement robust design flows.
- Analyze and debug complex physical design issues, including timing, power, and physical verification failures.
- Contribute to the continuous improvement of design processes and methodologies.
- Document design specifications, methodologies, and results clearly and concisely. - 応募資格/応募条件
- Required Skills & Experience :
- Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a related field.
- 5+ years of hands-on experience in digital backend IC design, with a strong focus on physical design and sign-off.
- Proven expertise in the full physical design flow: floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS/Antenna).
- Solid experience with power analysis (PDNA sign-off) and static timing analysis (STA).
- Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, RedHawk, Calibre).
- Experience in scripting languages (e.g., Tcl, Python, Perl) for design automation and flow development.
- Strong understanding of advanced CMOS process technologies and their impact on physical design.
- Excellent analytical and problem-solving skills, with a keen eye for detail.
- Business-level English proficiency, capable of technical discussions with international engineers.
- English communication skills.
Preferred Skills & Experience
- Experience in test chip design or IP development within a foundry environment.
- Familiarity with advanced technology nodes (e.g., 7nm, 5nm, 3nm).
- Knowledge of FinFET or GAAFET architectures.
- Experience with custom layout design or standard cell library development.
- Prior experience in developing custom design methodologies or CAD utilities.
- Understanding of reliability issues (e.g., EM, IR drop, ESD) from a physical design perspective.
- Project leadership or mentoring experience.
Desired Personality Traits
- Proactive and self-motivated, with a strong drive to innovate and solve complex technical challenges.
- Highly collaborative, able to work effectively with cross-functional teams across different geographies.
- Detail-oriented and committed to delivering high-quality, reliable designs.
- Continuously eager to learn and adapt to new technologies and methodologies.
- Strong communication skills to articulate complex technical concepts clearly. - 雇用形態
- 正社員
【試用期間】 3ヶ月（※労働条件は本採用と同じです） - 給与
- スキル・ご経験によって応相談
- 昇給
- 有
- 勤務地
- Albany, New York, Santa Clara, California, Tokyo, Japan, or Chitose, Japan
- 勤務時間
- フレックスタイム制（フルフレックス）
※1日の標準労働時間 7時間30分
※標準労働時間帯 9:00～17:30（休憩60分） - 休日休暇
- ・完全週休2日制（土・日）、国民の祝日
・年次有給休暇（20日 入社初年度は入社した月に応じる日数の年次有給休暇を付与する）
・創立記念日（8/10）
・年末年始休暇
・慶弔休暇
・産前・産後休暇
・育児休暇
・介護休暇
※年間休日 120日 - 加入保険
- ・健康保険
・厚生年金
・雇用保険
・労災保険 - 待遇・手当
- ・通勤手当
・残業手当
- 各種制度
- OJTでの研修教育を想定
- 応募書類
- 履歴書、職務経歴書
- その他
- 屋内完全禁煙により受動喫煙対策を実施
- 選考プロセス
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以下はモデルケースですので、面接回数など若干変更する場合もあります。
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STEP 1Webエントリー
エントリーフォームよりご応募ください。
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STEP 2書類選考
いただいた情報をもとに選考を行います。
※合否に関わらず選考結果をご連絡します。 -
STEP 3一次面接
オンラインにて実施します。
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STEP 4最終面接
対面にて実施します。確認事項あり。
※ポジションによっては、面接回数が2回とは限りません。 -
STEP 5内定
※応募の秘密は厳守いたします。
※本情報は選考の目的以外には一切使用いたしません。
※書類審査～内定まで最短で2～3週間程度かかります。
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- お問い合わせ
- Rapidus株式会社
東京都千代田区麹町4丁目1番地 麹町ダイヤモンドビル 11階
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